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19-2913; Rev 0; 8/03
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches
General Description
The MAX9392/MAX9393 dual 2 x 2 crosspoint switches perform high-speed, low-power, and low-noise signal distribution. The MAX9392/MAX9393 multiplex one of two differential input pairs to either or both low-voltage differential signaling (LVDS) outputs for each channel. Independent enable inputs turn on or turn off each differential output pair. Four LVCMOS/LVTTL logic inputs (two per channel) control the internal connections between inputs and outputs. This flexibility allows for the following configurations: 2 x 2 crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater. This makes the MAX9392/MAX9393 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the commonmode voltage exceeds the specified range. The MAX9392 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9393 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs. Ultra-low 98ps(P-P) (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in highspeed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less than 67ps (max) skew between channels. LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS outputs drive 100 loads. The MAX9392/MAX9393 are offered in 5mm x 5mm thin QFN with exposed paddle and 32-pin TQFP packages and operate over the extended temperature range (-40C to +85C). Also see the MAX9390/MAX9391 for the crossflow version.
Features
o 1.5GHz Operation with 250mV Differential Output Swing o 2psRMS (max) Random Jitter o AC Specifications Guaranteed for 150mV Differential Input o Signal Inputs Accept Any Differential Signaling Standard o LVDS Outputs for Clock or High-Speed Data o High-Level Input Fail-Safe Detection (MAX9392) o Low-Level Input Fail-Safe Detection (MAX9393) o +3.0V to +3.6V Supply Voltage Range o LVCMOS/LVTTL Logic Inputs Control Signal Routing
MAX9392/MAX9393
Ordering Information
PART MAX9392EHJ MAX9392ETJ* MAX9393EHJ MAX9393ETJ* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP 32 Thin QFN 32 TQFP 32 Thin QFN
*Future product--contact factory for availability.
Pin Configurations
TOP VIEW
ASEL1 ASEL0 INA1 INA1 INA0 INA0 26 GND 25 24 VCC 23 OUTA0 22 OUTA0 21 ENA0 20 GND 19 OUTA1 18 OUTA1 17 ENA1 9 ENB1 10 OUTB1 11 OUTB1 12 GND 13 ENB0 14 OUTB0 15 OUTB0 16 VCC VCC
32 GND 1 INB0 2 INB0 3 BSEL0 4
31
30
29
28
27
Applications
High-Speed Telecom/Datacom Equipment Central-Office Backplane Clock Distribution DSLAM Protection Switching Fault-Tolerant Systems
Functional Diagram and Typical Operating Circuit appear at end of data sheet.
VCC 5 INB1 6 INB1 7 BSEL1 8
MAX9392 MAX9393
TQFP
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, _SEL_ to GND..........................................-0.3V to (VCC + 0.3V) IN_ _ to IN_ _ ..........................................................................3V Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous Continuous Power Dissipation (TA = +70C) 32-Pin TQFP (derate 13.1mW/C above +70C).............................................................1047mW 32-Pin 5mm x 5mm Thin QFN (derate 21.3mW/C above +70C).............................................................1702mW Junction-to-Ambient Thermal Resistance in Still Air 32-Pin TQFP............................................................+76.4C/W 32-Pin 5mm x 5mm Thin QFN....................................+47C/W Junction-to-Case Thermal Resistance 32-Pin 5mm x 5mm Thin QFN......................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, EN_ _ = VCC, VCM = 0.05V to (VCC - 0.6V) (MAX9392), VCM = 0.6V to (VCC - 0.05V) (MAX9393), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current DIFFERENTIAL INPUTS (IN_ _, IN_ _) Differential Input Voltage Input Common-Mode Range Input Current LVDS OUTPUTS (OUT_ _, OU T _ _) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States VOD VOD VOS VOS RL = 100, Figure 2 Figure 2 Figure 2 Figure 2 1.125 250 350 1.0 1.25 1.0 450 50 1.375 50 mV mV V mV VID VCM IIN_ _, IIN_ _ VILD > 0 and VIHD < VCC, Figure 1 MAX9392 MAX9393 MAX9392 MAX9393 |VID| < 3.0V |VID| < 3.0V 0.1 0.05 0.6 -50 -10 3.0 VCC - 0.6 VCC - 0.05 +10 +90 V V A SYMBOL VIH VIL IIH IIL VIN = +2.0V to VCC VIN = 0 to +0.8V CONDITIONS MIN 2.0 0 0 0 TYP MAX VCC 0.8 20 10 UNITS V V A A
LVCMOS/LVTTL INPUTS (EN_ _, _SEL_)
2
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Anything-to-LVDS Dual 2 x 2 Crosspoint Switches
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, EN_ _ = VCC, VCM = 0.05V to (VCC - 0.6V) (MAX9392), VCM = 0.6V to (VCC - 0.05V) (MAX9393), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Output Short-Circuit Current (Either Output Shorted to GND) Output Short-Circuit Current (Outputs Shorted Together) SUPPLY CURRENT Supply Current ICC RL = 100, EN_ _ = VCC 68 98 mA SYMBOL |IOS| |IOSB| CONDITIONS VID = 100mV (Note 4) VOUT_ _ or V OUT_ _ = 0 VOUT_ _ = V OUT_ _ = 0 MIN TYP 30 18 5.0 MAX 40 24 12 UNITS mA mA
MAX9392/MAX9393
VID = 100mV, VOUT_ _ = V OUT_ _ (Note 4)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, fIN < 1.34GHz, tR_IN = tF_IN = 125ps, RL = 100 1%, |VID| > 150mV, VCM = +0.075V to (VCC - 0.6V) (MAX9392 only), VCM = +0.6V to (VCC - 0.075V) (MAX9393 only), EN_ _ = VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, fIN = 1.34GHz, TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER _SEL_ to Switched Output Disable Time to Differential Output Low Enable Time to Differential Output High Switching Frequency Low-to-High Propagation Delay High-to-Low Propagation Delay Pulse Skew |tPLH - tPHL| Output-to-Output Skew Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (80% to 20%) Added Random Jitter Added Deterministic Jitter SYMBOL tSWITCH tPHD tPDH fMAX tPLH tPHL tSKEW tCCS tR tF tRJ tDJ Figure 3 Figure 4 Figure 4 VOD > 250mV Figures 1, 5 Figures 1, 5 Figures 1, 5 (Note 6) Figures 5, 6 (Note 7) Figures 1, 5; fIN = 100MHz Figures 1, 5; fIN = 100MHz fIN_ _ = 1.34GHz, clock pattern (Note 8) 1.34Gbps, 223 - 1 PRBS (Note 8) 60 112 112 1.5 294 286 2.2 410 402 17 4 142 145 574 555 104 67 185 185 2 98 CONDITIONS MIN TYP MAX 1.1 1.7 1.7 UNITS ns ns ns GHz ps ps ps ps ps ps psRMS psP-P
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except VID, VOD, and VOD. Current into the device defined as positive. Current out of the device defined as negative. DC parameters tested at TA = +25C and guaranteed by design and characterization for TA = -40C to +85C. Current through either output. Guaranteed by design and characterization. Limits set at 6 sigma. tSKEW is the magnitude difference of differential propagation delays for the same output over same conditions. tSKEW = |tPHL - tPLH|. Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition, under the same conditions. Note 8: Device jitter added to the differential input signal. _______________________________________________________________________________________ 3
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
Typical Operating Characteristics
(VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, fIN = 1.34GHz, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9392 toc01
OUTPUT AMPLITUDE vs. FREQUENCY
MAX9392 toc02
OUTPUT RISE AND FALL TIMES vs. TEMPERATURE
fIN = 100MHz
MAX9392 toc03
80 75 SUPPLY CURRENT (mA) 70 65 60 VCC = +3.0V 55 50 -40 -15 10 35 60 VCC = +3.6V
400 350 OUTPUT AMPLITUDE (mV) 300 250 200 150 100 50 0
180 170 RISE/FALL TIME (ps) 160 150
VCC = +3.3V
tF 140 130 120 tR
85
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 FREQUENCY (GHz)
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
PROPAGATION DELAY vs. TEMPERATURE
440 PROPAGATION DELAY (ps) 430 420 410 400 390 380 370 360 350 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX9392 toc04
MAX9392 DIFFERENTIAL INPUT CURRENT vs. TEMPERATURE
VIN = 3.0V
MAX9392 toc05
MAX9393 DIFFERENTIAL INPUT CURRENT vs. TEMPERATURE
MAX9392 toc06
450
10 5 0 INPUT CURRENT (A) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50
70 60 INPUT CURRENT (A) 50 40 30 20 10 0 VIN = 0.3V -40 -15 10 35 60 VIN = 3.2V
VIN = 0.1V
-40
-15
10
35
60
85
85
TEMPERATURE (C)
TEMPERATURE (C)
MAX9392 INPUT CURRENT vs. VIHD
MAX9392 toc07
MAX9393 INPUT CURRENT vs. VILD
70 60 INPUT CURRENT (A) IN_ _ OR IN_ _ = VCC
MAX9392 toc08
10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 IN_ _ OR IN_ _ = GND
80
INPUT CURRENT (A)
VCC = +3V
50 40 30 20 10 0 -10 VCC = +3V VCC = +3.6V
VCC = +3.6V
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 VIHD (V)
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 VILD (V)
4
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Anything-to-LVDS Dual 2 x 2 Crosspoint Switches
Pin Description
PIN 1, 12, 20, 25 2 NAME GND Ground LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Noninverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Inverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). Input Select for B0 Output. Selects the differential input to reproduce at the B0 differential outputs. Connect BSEL0 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL0 to VCC to select the INB1 (INB1) set of inputs. An internal 435k resistor pulls BSEL0 low when unconnected. Power-Supply Input. Bypass each VCC to GND with 0.1F and 0.01F ceramic capacitors. Install both bypass capacitors as close to the device as possible, with the 0.01F capacitor closest to the device. LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Noninverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Inverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). Input Select for B1 Output. Selects the differential input to reproduce at the B1 differential outputs. Connect BSEL1 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL1 to VCC to select the INB1 (INB1) set of inputs. An internal 435k resistor pulls BSEL1 low when unconnected. B1 Output Enable. Drive ENB1 high to enable the B1 LVDS outputs. An internal 435k resistor pulls ENB1 low when unconnected. B1 LVDS Inverting Output. Connect a 100 termination resistor between OUTB1 and OUTB1 at the receiver inputs to ensure proper operation. B1 LVDS Noninverting Output. Connect a 100 termination resistor between OUTB1 and OUTB1 at the receiver inputs to ensure proper operation. B0 Output Enable. Drive ENB0 high to enable the B0 LVDS outputs. An internal 435k resistor pulls ENB0 low when unconnected. B0 LVDS Inverting Output. Connect a 100 termination resistor between OUTB0 and OUTB0 at the receiver inputs to ensure proper operation. B0 LVDS Noninverting Output. Connect a 100 termination resistor between OUTB0 and OUTB0 at the receiver inputs to ensure proper operation. FUNCTION
MAX9392/MAX9393
INB0
3
INB0
4 5, 16, 24, 29 6
BSEL0
VCC
INB1
7
INB1
8
BSEL1
9 10 11 13 14 15
ENB1 OUTB1 OUTB1 ENB0 OUTB0 OUTB0
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5
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
Pin Description (continued)
PIN 17 18 19 21 22 23 NAME ENA1 OUTA1 OUTA1 ENA0 OUTA0 OUTA0 FUNCTION A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435k resistor pulls ENA1 low when unconnected. A1 LVDS Inverting Output. Connect a 100 termination resistor between OUTA1 and OUTA1 at the receiver inputs to ensure proper operation. A1 LVDS Noninverting Output. Connect a 100 termination resistor between OUTA1 and OUTA1 at the receiver inputs to ensure proper operation. A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435k resistor pulls ENA0 low when unconnected. A0 LVDS Inverting Output. Connect a 100 termination resistor between OUTA0 and OUTA0 at the receiver inputs to ensure proper operation. A0 LVDS Noninverting Output. Connect a 100 termination resistor between OUTA0 and OUTA0 at the receiver inputs to ensure proper operation. LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Noninverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Inverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). Input Select for A0 Output. Selects the differential input to reproduce at the A0 differential outputs. Connect ASEL0 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL0 to VCC to select the INA1 (INA1) set of inputs. An internal 435k resistor pulls ASEL0 low when unconnected. LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Noninverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). LVDS/HSTL (MAX9392) or LVPECL/CML (MAX9393) Inverting Input. An internal 128k resistor to VCC pulls the input high when unconnected (MAX9392). An internal 68k resistor to GND pulls the input low when unconnected (MAX9393). Input Select for A1 Output. Selects the differential input to reproduce at the A1 differential outputs. Connect ASEL1 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL1 to VCC to select the INA1 (INA1) set of inputs. An internal 435k resistor pulls ASEL1 low when unconnected. Exposed Paddle (QFN Package Only). Connect to GND for optimal thermal and EMI characteristics.
26
INA0
27
INA0
28
ASEL0
30
INA1
31
INA1
32 --
ASEL1 EP
6
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Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
VIN_ _ VID = 0 VIN_ _ tPLH VOUT_ _ VOD = 0 VOUT_ _ VOD = 0 tPHL VID = 0 VILD VIHD
OUT_ _ 1/4 MAX9392/MAX9393 RL/2 IN_ _
VOD
VOS IN_ _ RL/2
80% 50% 20% tR VOD = 0
80% 50% VOD = 0 20% tF
EN_ _ = HIGH VID = VIN_ _ - VIN_ _
OUT_ _
VOD = VOD - VOD* VOS = VOS - VOS* VOD AND VOS ARE MEASURED WITH VID = +100mV VOD* AND VOS* ARE MEASURED WITH VID = -100mV
VID = VIN_ _ - VIN_ _ VOD = VOUT_ _ - VOUT_ _ tPLH AND tPHL MEASURED FOR ANY COMBINATION OF _SEL0 AND _SEL1.
Figure 1. Output Transition Time and Propagation Delay Timing Diagram
Figure 2. Test Circuit for VOD and VOS
IN_0 VID = 0 IN_0 IN_1 VID = 0 IN_1
VIHD VILD VIHD VILD
VIH 1.5V _SEL_ OUT_ _ IN_0 OUT_ _ tSWITCH EN_0 = EN_1 = HIGH VID = VIN_ _ - VIN_ _ tSWITCH VOD = 0 IN_1 VOD = 0 IN_0 1.5V VIL
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
_______________________________________________________________________________________
7
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
OUT_ _ 1/4 MAX9392/MAX9393 IN_ _ IN_ _ RL/2 PULSE GENERATOR CL 50 RL = 100 1% CL = 1.0pF OUT_ _ VOUT_ _ WHEN VID = -100mV VOUT_ _ WHEN VID = +100mV +1.25V VOUT_ _ WHEN VID = +100mV VOUT_ _ WHEN VID = -100mV CL RL/2 VEN_ _
1.5V
1.5V
3V 0
tPHD 50%
tPDH 50%
50% tPHD VID = VIN_ _ - VIN_ _ tPDH
50%
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram
_SEL0 IN_0 IN_0 0 RL 1 PULSE GENERATOR 50 50 0 IN_1 IN_1 1 CL RL OUT_1 CL OUT_0 CL OUT_0
MAX9392 MAX9393
CL OUT_1
_SEL1 EN_0 = EN_1 = HIGH 1 CHANNEL SHOWN RL = 100 1% CL = 1.0pF
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
8
_______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
VOUT_0 VOD = 0 VOUT_0 tCCS VOUT_1 VOD = 0 VOUT_1 VOD = VOUT_ _ - VOUT_ _ tCCS MEASURED WITH _SEL0 = _SEL1 = HIGH OR LOW (1:2 SPLITTER CONFIGURATION). IN_0 OUT_0 OR OUT_1 IN_1 VOD = 0 tCCS IN_1 2 x 2 CROSSPOINT OUT_1 VOD = 0 IN_0 OUT_0
Figure 6. Output Channel-to-Channel Skew
2:1 MUX
Detailed Description
The LVDS interface standard provides a signaling method for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 standard. LVDS utilizes a lower voltage swing than other communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9392/MAX9393 1.5GHz dual 2 x 2 crosspoint switches optimize high-speed, low-power, point-topoint interfaces. The MAX9392 accepts LVDS and HSTL signals, while the MAX9393 accepts LVPECL and CML signals. Both devices route the input signals to either or both LVDS outputs. When configured as a 1:2 splitter, the outputs repeat the selected inputs. This configuration creates copies of signals for protection switching. When configured as a repeater, the device operates as a two-channel buffer. Repeating restores signal amplitude, allowing isolation of media segments or longer media drive. When configured as a 2:1 mux, select primary or backup signals to provide a protection-switched, fault-tolerant application.
OUT_0 IN_0 OR IN_1 OUT_1
1:2 SPLITTER
IN_0
OUT_0
IN_1 DUAL REPEATER
OUT_1
Figure 7. Programmable Configurations
Select Function
The _SEL_ logic inputs control the input and output signal connections. Two logic inputs control the signal routing for each channel. _SEL0 and _SEL1 allow the devices to be configured as a differential crosspoint switch, 2:1 mux, dual repeater, or 1:2 splitter (Figure 7). See Table 1 for mode-selection settings (insert A or B for the _). Channels A and B possess separate select inputs, allowing different configurations for each channel.
Input Fail-Safe
The differential inputs of the MAX9392/MAX9393 possess internal fail-safe protection. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9392 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9393 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs.
Enable Function
The EN_ _ logic inputs enable and disable each set of differential outputs. Connect EN_ 0 to VCC to enable the OUT_0/OUT_0 differential output pair. Connect EN_0 to GND to disable the OUT_0/OUT_0 differential output pair. The differential output pairs assert to a differential low condition when disabled.
9
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Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
Table 1. Input/Output Function Table
_SEL0 0 0 1 1 _SEL1 0 1 0 1 OUT_0 / OUT_0 IN_0 / IN_0 IN_0 / IN_0 IN_1 / IN_1 IN_1 / IN_1 OUT_1 / OUT_1 IN_0 / IN_0 IN_1 / IN_1 IN_0 / IN_0 IN_1 / IN_1 MODE 1:2 splitter Repeater Switch 1:2 splitter
Applications Information
Differential Inputs
The MAX9392/MAX9393 inputs accept any differential signaling standard within the specified common-mode voltage range. The fail-safe feature detects commonmode input signal levels and generates a differential output low condition for undriven inputs or when the common-mode voltage exceeds the specified range. Leave unused inputs unconnected or connect to VCC for the MAX9392 or to GND for the MAX9393.
Output Termination
Terminate LVDS outputs with a 100 resistor between the differential outputs at the receiver inputs. LVDS outputs require 100 termination for proper operation. Ensure that the output currents do not exceed the current limits specified in the Absolute Maximum Ratings. Observe the total thermal limits of the MAX9392/ MAX9393 under all operating conditions.
Cables and Connectors
Use matched differential impedance for transmission media. Use cables and connectors with matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects.
Expanding the Number of LVDS Output Ports
Cascade devices to make larger switches. Consider the total propagation delay and total jitter when determining the maximum allowable switch size.
Power-Supply Bypassing
Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible. Install the 0.01F capacitor closest to the device.
Board Layout
Use a four-layer printed circuit (PC) board providing separate signal, power, and ground planes for highspeed signaling applications. Bypass VCC to GND as close to the device as possible. Install termination resistors as close to receiver inputs as possible. Match the electrical length of the differential traces to minimize signal skew.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9392/MAX9393. Connect each input and output to a 50 characteristic impedance trace. Maintain the distance between differential traces and eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode noise immunity. Minimize the number of vias on the differential input and output traces to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
10
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Anything-to-LVDS Dual 2 x 2 Crosspoint Switches
Typical Operating Circuit
+3.0V TO +3.6V 0.1F 0.01F VCC Z0 = 50 100 Z0 = 50 INA0 INA1 INA1 INB0 INB0 INB1 INB1 OUTB0 Z0 = 50 OUTA1 Z0 = 50 OUTA1 Z0 = 50 INA0 OUTA0 Z0 = 50 100
MAX9392/MAX9393
MAX9392 MAX9393
OUTA0
Z0 = 50 LVDS RECEIVER
MAX9173
ENA0 ENA1 ENB0 ENB1 LVCMOS/LVTTL LOGIC INPUTS ASEL0 OUTB1 ASEL1 BSEL0 BSEL1 GND GND GND GND Z0 = 50 OUTB1 Z0 = 50 OUTB0 Z0 = 50
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11
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
Functional Diagram Pin Configurations (continued)
TOP VIEW
ASEL1 INA1 INA1 INA0 INA0 26 0
INA0
MAX9392 MAX9393
OUTA0 OUTA0 GND 1 INB0 2 INB0 3 BSEL0 4
32
31
30
29
28
27
GND 25 24 VCC 23 OUTA0 22 OUTA0 21 ENA0 20 GND 19 OUTA1 18 OUTA1 17 ENA1 16 VCC
1
ENA0 ASEL0
INA1 INA1 1 OUTA1 OUTA1 ENA1 ASEL1 INB0 OUTB0 OUTB0 ENB0 BSEL0 INB1 OUTB1 OUTB1 ENB1 BSEL1 1 INB1 1 0 INB0
VCC 5 INB1 6 INB1 7 BSEL1 8 9 ENB1 10 OUTB1 11 OUTB1
MAX9392 MAX9393
0
*EXPOSED PADDLE 12 GND 13 ENBO 14 OUTB0 15 OUTB0
THIN QFN (5mm x 5mm)
*CONNECT EXPOSED PADDLE TO GND.
VCC
INA0
0
Chip Information
TRANSISTOR COUNT: 1565 PROCESS: Bipolar
12
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ASEL0
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX9392/MAX9393
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
______________________________________________________________________________________
13
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches MAX9392/MAX9393
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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